1. Field of the Invention
The present invention relates to a circuit for controlling a pulse width, and more particularly to, a circuit for controlling a pulse width of a column address select signal.
2. Discussion of Related Art
Recently, a high speed DRAM or DDR has been used in a graphic field. A pulse width, especially a pulse width of a column address select signal remarkably influences an operation of the device.
The DRAM for graphic operated in various domains of low frequency to high frequency has a very wide operation frequency domain, which causes many problems. Especially, the column address select signal must have an appropriate pulse width for each operation frequency so that DRAM data can be stably read and written. It is thus very important to control the pulse width of the column address select signal according to the operation frequency. In general, the pulse width of the column address select signal is preset as a predetermined value or controlled by an external clock.
A method for setting a pulse width of a column address select signal as a predetermined value generates a predetermined width of pulse regardless of tCK, namely a frequency. However, a standard for controlling the pulse width is ambiguous. When the pulse width is set at a low frequency, tCCD or tWTR is generated in a high frequency operation, to cause operation failure. Conversely, when the pulse width is set at a high frequency, the pulse width is too narrow to deteriorate tWR. Accordingly, data are not sufficiently written on a DRAM cell.
A method for controlling a column address select signal according to an external clock is not sensitive to variations of a process, voltage and temperature, and thus is relatively stable at a high frequency. However, the column address select signal has a narrow pulse width corresponding to half of a pulse width of the external clock. Differently from a DDR1, a DDR2 SDRAM maintains 2tCK of tCCD, and thus the column address select signal has a pulse width larger than half of the pulse width of the external clock (maximally, two times). Therefore, the DDR2 SDRAM cannot increase an operational margin. In addition, when the column address select signal is controlled according to the external clock, the pulse width of the column address select signal is large enough at a low frequency to cause problems in a normal operation or a test.